R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 710

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 682 of 1164
REJ09B0321-0200
Bit
6
Bit Name
TEND
Initial
Value
1
R/W
R/(W)* Transmit End
Description
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
•
1: End of transmission
[Setting conditions]
•
•
•
Note:
TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR*
TEND is set to 1 when the chip is a power-on
reset
TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
1. Do not use this bit as a transmit end flag
when the DMAC writes data to SCFTDR
due to a TXI interrupt request.
1