R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 356

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.3.9
DMCNTB enables or disables DMA transfer, clears the DMA transfer enable bit, and also clears
the internal state. In addition, this register can check the status of a DMA request.
Rev. 2.00 Sep. 07, 2007 Page 328 of 1164
REJ09B0321-0200
Bit
31 to 25 
24
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Control Register B (DMCNTB)
Bit Name
DEN
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
29
13
—
—
R
R
0
0
Initial
Value
All 0
0
28
12
—
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R/W
26
10
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Transfer Enable
This bit is used to enable or disable DMA transfer on
the corresponding channel.
Clearing this bit to "0" disables DMA transfer.
Setting this bit to "1" enables DMA transfer. For the
activation of DMA transfer, see section 11.4.3, DMA
Activation.
Even when this bit is clear, the input of a DMA request
to the DMAC can change the value of the DMA
request bit (DREQ).
When the DMA transfer enable clear bit (ECLR) is set
to "1", this bit is automatically cleared to "0" on
detection of the DMA transfer end condition.
Clearing this bit to "0" during DNA transfer can be
used to stop channel operation at the end of the
current single operand transfer. For details, see
section 11.6, Suspending, Restarting, and Stopping of
DMA Transfer.
0: DMA transfer disabled
1: DMA transfer enabled
25
—
—
R
R
0
9
0
ECLR
DEN
R/W
R/W
24
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
DREQ
DSCLR
R/W
R/W
16
0
0
0