R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 875

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.5.4
The ABACK0 is a 16-bit read/conditionally-write registers. This register is used to signal to the
CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded
the RCAN-ET sets the corresponding bit in the ABACK register. The CPU may clear the Abort
Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. An
ABACK bit position is set by the RCAN-ET to acknowledge that a TXPR bit has been cleared by
the corresponding TXCR bit.
• ABACK0
Note: * Only when writing a '1' to clear.
Bit 15 to 1 — Notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has
no effect and always read back as a '0'.
Bit[15:1]:ABACK0 Description
0
1
Initial value:
R/W:
Bit:
Abort Acknowledge Register 0 (ABACK0)
R/W*
15
0
R/W*
14
0
[Clearing Condition] Writing '1' (Initial value)
Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition] Completion of transmission cancellation for corresponding
mailbox
R/W*
13
0
R/W*
12
0
R/W*
11
0
R/W*
10
0
R/W*
9
0
ABACK0[15:1]
R/W*
8
0
R/W*
Section 19 Controller Area Network (RCAN-ET)
7
0
Rev. 2.00 Sep. 07, 2007 Page 847 of 1164
R/W*
6
0
R/W*
5
0
R/W*
4
0
R/W*
3
0
REJ09B0321-0200
R/W*
2
0
R/W*
1
0
—
0
0
0