R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 726

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR).
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of
receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is
initialized to H'0000 by a power on reset or in deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 698 of 1164
REJ09B0321-0200
Bit
0
Bit
15 to 13
12 to 8
7 to 5
4 to 0
Initial value:
R/W:
Bit:
Bit Name
LOOP
Bit Name
—
T[4:0]
—
R[4:0]
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
0
Initial
Value
All 0
00000
All 0
00000
12
R
0
11
R
0
R/W
R/W
R/W
R
R
R
R
T[4:0]
10
R
0
Description
Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
T4 to T0 bits indicate the quantity of non-transmitted
data stored in SCFTDR. H'00 means no transmit data,
and H'10 means that SCFTDR is full of transmit data.
Reserved
These bits are always read as 0. The write value should
always be 0.
R4 to R0 bits indicate the quantity of receive data
stored in SCFRDR. H'00 means no receive data, and
H'10 means that SCFRDR full of receive data.
R
0
9
R
0
8
—
R
0
7
—
R
0
6
—
R
0
5
R
0
4
R
0
3
R[4:0]
R
0
2
R
0
1
R
0
0