R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 633
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 633 of 1196
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Notes: 1. If the clock input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
13.3.6
TCSR displays status flags, and controls compare match output.
• TCSR_0
• TCSR_1
Channel
All
2. To use the external clock, the function of the corresponding pin should be selected
Timer Control/Status Register (TCSR)
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
using the pin function controller (PFC). For details, see section 23, Pin Function
Controller (PFC).
Bit 2
CKS2
1
1
1
Bit 1
CKS1
0
1
1
TCR
Initial value:
Initial value:
Note:
Note:
Bit 0
CKS0
1
0
1
R/W:
R/W:
Bit:
Bit:
* Only 0 can be written to this bit, to clear the flag.
* Only 0 can be written to this bit, to clear the flag.
CMFB
R/(W)*R/(W)*R/(W)* R/W
CMFB
R/(W)*R/(W)*R/(W)*
Bit 1
ICKS1
0
0
7
7
CMFA
CMFA
TCCR
0
0
6
6
Bit 0
ICKS0
OVF
OVF
0
0
5
5
ADTE
Description
Uses external clock. Counts at rising edge*
Uses external clock. Counts at falling edge*
Uses external clock. Counts at both rising and falling
edges*
—
R
0
0
4
4
R/W
R/W
2
.
3
0
3
0
OS[3:2]
OS[3:2]
Rev. 2.00 Sep. 07, 2007 Page 605 of 1164
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
OS[1:0]
OS[1:0]
Section 13 8-Bit Timers (TMR)
R/W
R/W
0
0
0
0
REJ09B0321-0200
2
2
.
.
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