MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 993

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

12.12.2.1 BCH ECC Page Organization.
For NAND boot, ROM restricts the size of a BCH data block to 512 bytes. The first data
block is called block 0 and the rest of the blocks are called block N. Separate ECC levels
can be used for block 0 and block N. The metadata bytes should be located at the beginning
of a page, starting at byte 0, followed by data block 0, followed by ECC bytes for data block
0, followed by block 1 and its ECC bytes, and so on until N data blocks. The ECC level for
block 0 can be different from the ECC level of rest of the blocks. Metadata bytes can be 0.
For NAND boot, with page size restrictions and data block size restricted to 512 bytes, only
few combinations of ECC for block 0 and block N are possible.
The number of ECC bits required for a data block is calculated using (ECC_Correction_Level
* 13) bits.
In the above layout, the ECC size for EccB0 and EccBN should be selected to not exceed
a total page size of 2112 bytes. EccB0 and EccBN can be one of 2, 4, 6, 8, 10, 12, 14, 16,
18, 20 bits ECC correction level. The total bytes would then be:
There are four data blocks of 512 bytes, each in a page of 2K page sized NAND. The values
of EccB0 and EccBN should be such that the above calculation would not result in a value
greater than 2112 bytes.
Different NAND manufacturers have different sizes for a 4K page, 4314 bytes is typical.
Freescale Semiconductor, Inc.
[M + (data_block_size * 4) + ([EccB0 + (EccBN * 3)] * 13) / 8] <= 2112;
M=metadata bytes and data_block_size is 512.
[M + (data_block_size * 8) + ([EccB0 + (EccBN * 7)] * 13) / 8] <= 4314;
M=metadata bytes and data_block_size is 512.
M
M
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 12-15. Valid layout for 2112 bytes sized page
Figure 12-16. Valid layout for 4K bytes sized page
512 bytes
512 bytes
512 bytes
Block 0
Block 4
Block 0
EccBN
EccB 0
EccB 0
512 bytes
512 bytes
512 bytes
Block 1
Block 5
Block 1
EccBN
EccBN
EccBN
512 bytes
512 bytes
512 bytes
Block 2
Block 6
Block 2
EccBN
EccBN
EccBN
512 bytes
512 bytes
512 bytes
Block 3
Block 3
Block 7
EccBN
EccBN
EccBN
Chapter 12 Boot Modes
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