MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 363

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.5.3 AHB to APBH Bridge Control and Status Register 2
The APBH CTRL 2 provides channel error interrupts generated by the AHB to APBH
DMA.
HW_APBH_CTRL2: 0x020
HW_APBH_CTRL2_SET: 0x024
HW_APBH_CTRL2_CLR: 0x028
HW_APBH_CTRL2_TOG: 0x02C
This register contains the per channel interrupt status bits and the per channel interrupt
enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller.
EXAMPLE
BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0);
BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0;
Address:
Freescale Semiconductor, Inc.
Reset
CMDCMPLT_IRQ
CMDCMPLT_IRQ
Bit
W
R
CH1_
CH0_
Field
1
0
31
0
(HW_APBH_CTRL2)
HW_APBH_CTRL2
30
0
Interrupt request status bit for APBH DMA channel 1. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 0. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH_CTRL1 field descriptions (continued)
28
0
8000_4000h base + 20h offset = 8000_4020h
27
0
26
0
25
0
// use bitfield write macro
// or, assign to register struct's bitfield
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
24
0
Description
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
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