MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1465

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

1. Address trap IRQ. IRQ will be asserted if any transaction address hit within the
pre-configured address range.
2. Address range inversion IRQ. IRQ will be asserted if any transaction address hit outside
the pre-configured address range.
3. Max latency threshold IRQ: IRQ will be asserted if maximum latency is above the value
defined in the threshold register.
4. Bus error IRQ: IRQ will be asserted if any AXI transaction triggers an error response.
21.3 Programmable Registers
PERFMON Hardware Register Format Summary
Freescale Semiconductor, Inc.
8000_6000
8000_6010
8000_6020
8000_6030
8000_6040
8000_6050
8000_6060
8000_6070
8000_6080
8000_6090
8000_60A0
8000_60B0
Absolute
address
(hex)
PerfMon Control Register (HW_PERFMON_CTRL)
PerfMon Master Enable Register
(HW_PERFMON_MASTER_EN)
PerfMon Trap Range Low Address Register
(HW_PERFMON_TRAP_ADDR_LOW)
PerfMon Trap Range High Address Register
(HW_PERFMON_TRAP_ADDR_HIGH)
PerfMon Latency Threshold Register
(HW_PERFMON_LAT_THRESHOLD)
PerfMon AXI Active Cycle Count Register
(HW_PERFMON_ACTIVE_CYCLE)
PerfMon Transfer Count Register
(HW_PERFMON_TRANSFER_COUNT)
PerfMon Total Latency Count Register
(HW_PERFMON_TOTAL_LATENCY)
PerfMon Total Data Count Register
(HW_PERFMON_DATA_COUNT)
PerfMon Maximum Latency Register
(HW_PERFMON_MAX_LATENCY)
PerfMon Debug Register (HW_PERFMON_DEBUG)
PerfMon Version Register (HW_PERFMON_VERSION)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_PERFMON memory map
Chapter 21 Performance Monitor (PERFMON)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
C000_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0001h
0100_0000h
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