MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1034
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
- MCIMX283DVM4B PDF datasheet #2
- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
Programmable Registers
13.3.9 DCP Work Packet 0 Status Register (HW_DCP_PACKET0)
This register displays the values for the current work packet offset 0x00 (Next Command)
field.
The Work Packet Status Registers show the contents of the currently executing packet.
When the channels are inactive, the packet status register return 0. The register bits are fully
documented here to document the packet structure in memory.
Address:
Re-
13.3.10 DCP Work Packet 1 Status Register (HW_DCP_PACKET1)
This register displays the values for the current work packet offset 0x04 (control) field.
This register shows the contents of the Control0 register from the packet being processed.
Address:
1034
set
Reset
Bit
W
R
Bit
31
W
0
R
ADDR
Field
31 0
30
0
31
0
29
0
HW_DCP_PACKET1
HW_DCP_PACKET0
28
0
30
0
Next Pointer Register,
27
0
26
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
28
0
TAG
23
0
HW_DCP_PACKET0 field descriptions
8002_8000h base + 90h offset = 8002_8090h
8002_8000h base + 80h offset = 8002_8080h
22
0
27
0
21
0
20
0
26
0
19
0
18
25
0
0
17
0
ADDR
16
24
0
0
15
0
Description
23
14
0
0
13
0
22
12
0
0
11
0
21
0
10
0
0
9
20
0
0
8
Freescale Semiconductor, Inc.
0
7
19
0
0
6
0
5
18
0
0
4
3
0
17
0
0
2
0
1
16
0
0
0
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