MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 485

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.5.110 APBH DMA channel 14 Semaphore Register
The APBH DMA channel 14 semaphore register is used to synchronize between the CPU
instruction stream and the DMA chain processing state.
Because channel 14 is not assigned to any peripheral, this register is of no practical usage
and just reserved for compatibility.
Address:
Re-
6.5.111 AHB to APBH DMA channel 14 Debug Information
This register gives debug visibility into the APBH DMA channel 14 state machine and
controls.
Because channel 14 is not assigned to any peripheral, this register is of no practical usage
and just reserved for compatibility.
Freescale Semiconductor, Inc.
set
Bit
W
R
INCREMENT_
31
0
PHORE
RSVD2
RSVD1
31 24
23 16
SEMA
Field
15 8
7 0
30
0
29
0
HW_APBH_CH14_SEMA
RSVD2
(HW_APBH_CH14_SEMA)
(HW_APBH_CH14_DEBUG1)
28
0
Reserved, always set to zero.
This read-only field shows the current (instantaneous) value of the semaphore counter.
Reserved, always set to zero.
The value written to this field is added to the semaphore count in an atomic way such that simultaneous
software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads
back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA
channel decrements the count on the same clock, then the count is incremented by a net one.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_APBH_CH14_SEMA field descriptions
23
0
22
0
21
0
8000_4000h base + 760h offset = 8000_4760h
PHORE
20
0
19
0
18
0
17
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
16
0
15
0
Description
14
0
13
0
RSVD1
12
0
11
0
10
0
0
9
0
8
0
7
INCREMENT_SEMA
0
6
0
5
0
4
3
0
0
2
0
1
485
0
0