MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1603

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.2.2.31.1.14
VLAN. This is an accelerator option. This bit is written by the uDMA. This bit means that
the frame has a VLAN tag. This bit is valid only if the L-bit is set.
26.2.2.31.1.15
IPV6 Frame. This bit is written by the uDMA. This bit indicates that the frame has a IPv6
frame type. If this bit is not set, it means that an IPv4 or other protocol frame was received.
This bit is valid only if the L-bit is set.
26.2.2.31.1.16
Pv4 Fragment.This is an accelerator option.This bit is written by the uDMA.This bit indicates
that the frame is an IPv4 fragment frame. This bit is only valid when the L-bit is set.
26.2.2.31.1.17
uDMA. This field is the sum of 32 bit words found within the IP and its following protocol
headers. If an IP datagram with an unknown protocol is found, the value is the length of
the IP header. If no IP frame or an erroneous IP header is found, the value is 0. The following
values are minimum values if no header options exist in the respective headers:
This field is only valid if the L-bit is set.
26.2.2.31.1.18
within the IP header of the frame. Only valid if "ICE" bit is 0. This bit is only valid if the
L-bit is set.
26.2.2.31.1.19
Internet payload checksum. This is an accelerator option. The one's complement sum of the
payload section of the IP frame. The sum is calculated over all data following the IP header
until the end of the IP payload. This field is valid only when the L-bit is set.
26.2.2.31.1.20
BD data has been updated by uDMA. This bit is written by the user (=0) and uDMA (=1).
26.2.2.31.1.21
It is only valid if the L-bit is set.
Freescale Semiconductor, Inc.
• ICMP/IP: 6 (5 IP header, 1 ICMP header)
• UDP/IP: 7 (5 IP header, 2 UDP header)
• TCP/IP: 10 (5 IP header, 5 TCP header)
Offset + A – Bit 2 VLAN
Offset + A – Bit 1 IPV6
Offset + A – Bit 0 FRAG
Offset + C – Bit [15:11] Header Length
Header length. This is an accelerator option. This field is written by the
Offset + C – Bit [7:0] Protocol Type
Protocol type. This is an accelerator option. The 8-Bit protocol field found
Offset + E – Bit [15:0] Payload Checksum
Offset + 0x10 – Bit 15 BDU
Last Buffer Descriptor Update Done. This bit indicates that all the last
1588 Timestamp [31:0]
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 26 Ethernet Controller (ENET)
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