MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 985

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

12.12.1.8 Firmware Configuration Block
The FCB is the first sector in the first good block. The FCB should be present at each search
stride of the search area. The search area contains copies of the FCB at each stride distance,
so in case the first NAND block becomes corrupted, the ROM will find its copy in the next
NAND block. The search area should span over at least two NAND blocks. The location
information of DBBT search area, FW1 and FW2 are all specified in the FCB. This case is
shown in more detail in
The layout of the first good page containing FCB is shown in the following figure.
The FCB is located on the first good page of the NAND; the minimum size of a page is
2112 bytes. The first 12 bytes of an FCB page are reserved and left blank (all zeros); the
next 512 bytes are reserved for FCB data. The remaining 512 bytes are available for software
ECC, and the rest are all zeros. FCB is protected using SEC-DED Hamming codes.
Freescale Semiconductor, Inc.
Figure 12-10. Expected NAND Layout for patch boot with search count = 2 and search
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 12-11. Layout of Boot Page Containing FCB
Firmware Layout on the
FCB Search Area
stride = 15*64 and valid DBBT
Parity Bits For FCB Data
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Bytes Left
FCB Data
Page 0
Page 1
Spare
Firmware Configuration Block
Firmware Configuration Block
NAND.
Boot Firmware 1
Boot Firmware 2
1036
2111
524
(FCB)
(FCB)
12
0
Chapter 12 Boot Modes
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