MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1424

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
20.2.1 Software Read Sequence
Reading OTP contents is relatively simple, because all OTP words are memory-mapped on
the APB space (see
except for the HW/SW capability, CUSTCAP, ROM and SRK shadow registers, which are
writable until the appropriate LOCK bit in OTP is set.
Due to the fuse-read architecture, the OTP banks must be open before they can be read.
This is accomplished as follows (the following does not apply to shadow registers, which
can be read at any time).
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1. Program the HCLK to a frequency up to the maximum allowable HCLK frequency.
2. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear.
3. Set HW_OCOTP_CTRL_RD_BANK_OPEN. This will kick the controller to put the
4. Poll for HW_OCOTP_CTRL_BUSY clear. When HW_OCOTP_CTRL_BUSY is clear
5. Once accesses are complete, clear HW_OCOTP_CTRL_RD_BANK_OPEN. Leaving
• HW_OCOTP_DATA Data register (32- bit) for OTP programming (writes).
• HW_OCOTP_CTRL_ADDR Address register (6-bit) for OTP programming (writes).
• HW_OCOTP_CTRL_BUSY Programming/write request/status handshake bit.
• HW_OCOTP_CTRL_ERROR Read/write access error status.
• HW_OCOTP_CTRL_RD_BANK_OPEN Status of OTP read availability (reads).
Note that this cannot exceed 200 MHz.
fuses into read mode. The controller will set HW_OCOTP_CTRL_BUSY until the
OTP contents are readable. Note that if there was a pending write (holding
HW_OCOTP_CTRL_BUSY) and HW_OCOTP_CTRL_RD_BANK_OPEN was set,
the controller would complete the write and immediately move into read operation
(keeping HW_OCOTP_CTRL_BUSY set while the banks are being opened).
and HW_OCOTP_CTRL_RD_BANK_OPEN is set, read the data from the appropriate
memory-mapped address. Note that this is not necessary for registers that are shadowed.
Reading before HW_OCOTP_CTRL_BUSY is cleared by the controller, will return
0xBADA_BADA and will result in the setting of HW_OCOTP_CTRL_ERROR.
Because opening banks takes approximately 33 HCLK cycles, immediate polling for
BUSY is not recommended.
the banks open will cause current drain.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Programmable Registers
for details). These registers are read-only,
Freescale Semiconductor, Inc.