MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1281

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

// generic DMA/GPMI/ECC descriptor struct, order sensitive!
//----------------------------------------------------------------------------
typedef struct {
} GENERIC_DESCRIPTOR;
//----------------------------------------------------------------------------
// allocate 7 descriptors for doing a NAND ECC Read
//----------------------------------------------------------------------------
GENERIC_DESCRIPTOR read[7];
//----------------------------------------------------------------------------
// DMA descriptor pointer to handle error conditions from psense checks
//----------------------------------------------------------------------------
unsigned int * dma_error_handler;
//----------------------------------------------------------------------------
// 7 byte NAND command and address buffer
// any alignment is ok, it is read by the GPMI DMA
//
//
//
//----------------------------------------------------------------------------
unsigned char nand_cmd_addr_buffer[7];
//----------------------------------------------------------------------------
// 4096 byte payload buffer used for reads or writes
// needs to be word aligned
//----------------------------------------------------------------------------
unsigned int read_payload_buffer[(4096/4)];
//----------------------------------------------------------------------------
// 412 byte auxiliary buffer used for reads
// needs to be word aligned
//----------------------------------------------------------------------------
unsigned int read_aux_buffer[(412/4)];
//----------------------------------------------------------------------------
// Descriptor 1: issue NAND read setup command (CLE/ALE)
//----------------------------------------------------------------------------
read[0].dma_nxtcmdar = &read[1];
read[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT
NAND
read[0].dma_bar = &nand_cmd_addr_buffer;
address
// 3 words sent to the GPMI
read[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE)
CS used
Freescale Semiconductor, Inc.
// DMA related fields
unsigned int dma_nxtcmdar;
unsigned int dma_cmd;
unsigned int dma_bar;
// GPMI related fields
unsigned int gpmi_ctrl0;
unsigned int gpmi_compare;
unsigned int gpmi_eccctrl;
unsigned int gpmi_ecccount;
unsigned int gpmi_data_ptr;
unsigned int gpmi_aux_ptr;
byte 0 is read setup command
bytes 1-5 is the NAND address
byte 6 is read execute command
BF_APBH_CHn_CMD_CMDWORDS
BF_APBH_CHn_CMD_WAIT4ENDCMD
BF_APBH_CHn_CMD_SEMAPHORE
BF_APBH_CHn_CMD_NANDWAIT4READY(0)
BF_APBH_CHn_CMD_NANDLOCK
BF_APBH_CHn_CMD_IRQONCMPLT
BF_APBH_CHn_CMD_CHAIN
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ);
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BV_FLD(GPMI_CTRL0, WORD_LENGTH,
BV_FLD(GPMI_CTRL0, LOCK_CS,
BF_GPMI_CTRL0_CS
BV_FLD(GPMI_CTRL0, ADDRESS,
BF_GPMI_CTRL0_ADDRESS_INCREMENT
BF_GPMI_CTRL0_XFER_COUNT
(1 + 5) |
(3)
(1)
(0)
(1)
(0)
(1)
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
// byte 0 read setup, bytes 1 - 5 NAND
8_BIT)
ENABLED)
(2)
NAND_CLE) |
(1)
(1 + 5);
|
|
|
|
|
|
|
// point to the next descriptor
// 1 byte command, 5 byte address
// send 3 words to the GPMI
// wait for command to finish
//
// prevent other DMA channels from
//
// follow chain to next command
// read data from DMA, write to
| // write to the NAND
|
|
| // must correspond to NAND
| // send command and address
taking over
before continuing
// 1 byte command, 5 byte
1281