MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2230
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
- MCIMX283DVM4B PDF datasheet #2
- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
Programmable Registers
HW_SPDIF_CTRL.RUN = 1; // start SPDIF conversion
Address:
2230
Reset
Reset
WORD_LENGTH
UNDERFLOW_
WAIT_END_
DMAWAIT_
CLKGATE
Bit
Bit
W
W
RSRVD1
RSRVD0
SFTRST
R
R
COUNT
29 21
20 16
FIFO_
XFER
Field
15 6
IRQ
31
30
5
4
3
31
15
1
0
HW_SPDIF_CTRL
30
14
1
0
Setting this bit to one forces a reset to the entire block and then gates the clocks off. This bit must be set to
zero for normal operation.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
First set the CLKGATE bit in the HW_CLKCTRL_SPDIF register to 1. Only then, set this bit to 1 to prevent
any extra samples from being transmitted. When removing clock gating, follow the reverse order: First reset
this CLKGATE bit to 0, and then reset the CLKGATE bit in the HW_CLKCTRL_SPDIF register to 0 .
Reserved
DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay before
each DMA request. This field acts as a throttle on the bandwidth consumed by the SPDIF block. This field
can be loaded by the DMA.
Reserved
Set this bit to a one if the SPDIF Transmitter should wait until the internal FIFO is empty before halting
transmission based on deassertion of RUN. Use in conjuntion with HW_SPDIF_STAT_END_XFER to
determine transfer completion
Set this bit to one to enable 16-bit mode. Set this bit to zero for 32-bit mode. In either case, the SPDIF frame
allows transmission of only 24 bits. In 16-bit mode, eight zeros will be appended to the LSB\'s of the input
sample; in 32-bit mode, the 24 MSB\'s of HW_SPDIF_DATA will be transmitted.
This bit is set by hardware if the FIFO underflows during SPDIF transmission. Reset this bit by writing a one
to the SCT clear address space and not by a general write.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
8005_4000h base + 0h offset = 8005_4000h
HW_SPDIF_CTRL field descriptions
27
11
RSRVD0
0
0
26
10
0
0
RSRVD1
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
1
20
0
4
0
Freescale Semiconductor, Inc.
DMAWAIT_COUNT
19
0
0
3
18
0
0
2
17
0
0
1
RUN
16
0
0
0
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