MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2096

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
33.4.11 LCDIF VSYNC Mode and Dotclk Mode Control Register3
This register is used to determine the vertical and horizontal wait counts.
This register determines the back porches of HSYNC and VSYNC signals when they are
generated by the block.
Address:
2096
Reset
Reset
HORIZONTAL_
VSYNC_ONLY
MUX_SYNC_
VERTICAL_
WAIT_CNT
WAIT_CNT
Bit
Bit
SIGNALS
W
W
RSRVD0
R
R
31 30
27 16
Field
15 0
29
28
31
15
RSRVD0
0
0
HW_LCDIF_VDCTRL3
(HW_LCDIF_VDCTRL3)
30
14
0
0
Reserved bits, write as 0.
When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13
and ENABLE with LCD_D12, otherwise these signals will go out on separate pins. This feature can be used
to maintain backward compatability with 37xx.
This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.
In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of
HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture
information begins.
In the VSYNC interface mode, wait for this number of CLK_DIS_LCDIFn cycles from the falling VSYNC
edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if
WAIT_FOR_VSYNC_EDGE is set. Minimum is CMD_SETUP+5. In the DOTCLK mode, it accounts for the
veritcal back porch lines plus the number of horizontal lines before the moving picture begins. The unit for
this parameter is inherently the same as the VSYNC_PERIOD_UNIT.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_LCDIF_VDCTRL3 field descriptions
27
11
0
0
8003_0000h base + A0h offset = 8003_00A0h
26
10
0
0
25
VERTICAL_WAIT_CNT
0
0
9
24
0
0
8
Description
HORIZONTAL_WAIT_CNT
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0