MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2242

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
data are put together to be a 32-bit word before written to the FIFO. The user can also
configure the register to get big-endian or little-endian and also half-word-swapped data in
the external memory. This operation is done when sample data are read out from the FIFO.
37.3 Operation
The main target of this block is to drive the linear image scanner sensors, especially the
TOSHIBA TCD1304DG linear image scanner sensor. To drive this sensor, three driving
signals are needed. In order to support other linear image scanner sensors, the driving signals
are generated by the PWM block which can improve the design flexibilities. Each PWM
instance can be configured as any type of cyclic signal. In order to keep synchronous with
the ADC block, the PWM can be configured to use the operation clock of ADC block to
generate the driving signals of external devices. When the high-speed ADC is started by
the ARM or DMA, it will enter the state to wait for a trigger to start sampling the analog
input source. There are three modes to generate this trigger signal. When configured as
PWM trigger mode, the PWM can generate the trigger signal with the operation clock to
trigger the high-speed ADC to start the sampling. This trigger signal can be generated by
any one of the PWM instances and is hard-wire connected to the high-speed ADC block.
In order to make it possible for adjusting the sampling point in order to improve the S/N
ratio of sample data, some delay cycles of operation clock can be added between the trigger
pulse and the time to start sampling. The number of delay cycles can be configured.
There is a 16x32 asynchronous FIFO inside the high-speed ADC with 32-bit width and
16-word depth. The sample data is formed as 32-bit word and then written to the FIFO.
When the data is read out, it is reformed to the correct endian and half-word-swapped type.
The APBH-DMA will then move the data to the external memory. It is flexible to configure
the DMA to put the sample data if there are some requirements about the data format in the
external memory, such as line strides, and so on. It is recommended to use one DMA
command for each sequence of sample data. So, in loop modes of the high-speed ADC,
many sequences of sample data need to be transferred to the external memory which will
need a DMA command link to conduct the task. The high-speed ADC will signify the DMA
to switch to the next command when one sequence is completed.
For general user cases, the design also provides software trigger mode and external trigger
mode. The sample data transferring is also done by the APBH-DMA.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2242
Freescale Semiconductor, Inc.