MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 151

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Reset
VECTOR_PITCH
BYPASS_FSM
NO_NESTING
ARM_RSE_
CLKGATE
Bit
W
RSRVD3
SFTRST
R
MODE
29 24
23 21
Field
31
30
20
19
18
15
0
14
0
When set to one, this bit causes a soft reset to the entire interrupt collector. This bit must be turned off for
normal operation.
0x0
0x1
When set to one, this bit causes all clocks within the interrupt collector to be gated off. NOTE: Do not set
this bit at the same time as SFTRST. Doing so, causes the soft reset to have no effect. Setting SFTRST will
cause the CLKGATE bit to set automatically four clocks later.
0x0
0x1
Always write zeroes to this bitfield.
When an interrupt occurs one of the 128 input requests becomes the winning bit number, i.e. 127. This bit
field selects one of eight constant multiplier values to multiply the winning bit number. The multiplied bit
number is added to the vector table base to become the vector address. 0x0 and 0x1 yield a multiplier of 4
bytes. 0x2 yields a multiplier of 8 bytes while 0x3 yields a multiplier of 12 bytes, that is, (8 + 4) bytes per
step.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Set this bit to one to bypass the FSM control of the request holding register and the vector address. With
this bit set to one, the vector address register is continuously updated as interrupt requests come in. Turn
off all enable bits and walk once through the software interrupts, observing the vector address changes. Set
to zero for normal operation. This control is included as a test mode, and is not intended for use by a real
application.
0x0
0x1
Set this bit to one disable interrupt level nesting, that is, higher priority interrupt interrupting lower priority.
For normal operation, set this bit to zero.
0x0
0x1
Set this bit to one enable the ARM-style read side effect associated with the vector address register. In this
mode, interrupt inservice is signalled by the read of the HW_ICOLL_VECTOR register to acquire the interrupt
vector address. Set this bit to zero for normal operation, in which the ISR signals inservice explicitly by
means of a write to the HW_ICOLL_VECTOR register.
13
0
RUN — Allow the interrupt collector to operate normally.
IN_RESET — Hold the interrupt collector in its reset state.
RUN — Enable clocks for normal operation of interrupt collector.
NO_CLOCKS — disable clocking within the interrupt collector.
DEFAULT_BY4 — one word pitch
BY4 — one word pitch
BY8 — two word pitch
BY12 — three word pitch
BY16 — four word pitch
BY20 — five word pitch
BY24 — six word pitch
BY28 — seven word pitch
NORMAL — Normal
BYPASS — no FSM handshake with CPU
NORMAL — Normal
NO_NEST — no support for interrupt nesting
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_ICOLL_CTRL field descriptions
11
0
10
0
0
9
RSRVD1
0
8
Description
0
7
0
6
5
0
Chapter 5 Interrupt Collector (ICOLL)
4
0
0
3
0
2
0
1
0
0
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