MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1784

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
28.4.2 PWM Channel 0 Active Register (HW_PWM_ACTIVE0)
The PWM Channel 0 Active Register specifies the active time and inactive time for Channel
0.
HW_PWM_ACTIVE0: 0x010
HW_PWM_ACTIVE0_SET: 0x014
HW_PWM_ACTIVE0_CLR: 0x018
HW_PWM_ACTIVE0_TOG: 0x01C
1784
PWM7_ENABLE
PWM6_ENABLE
PWM5_ENABLE
PWM4_ENABLE
PWM3_ENABLE
PWM2_ENABLE
PWM1_ENABLE
PWM0_ENABLE
CUTOFF_EN
PRESENT
OUTPUT_
RSRVD1
RSRVD2
PWM0_
21 10
Field
22
9
8
7
6
5
4
3
2
1
0
0 = PWM0 is not present in this product.
Reserved.
When asserted this bit enables the block to automatically Hi-Z state the outputs whenever the clkgate is
asserted. The default is disabled.
Reserved.
Enables PWM channel 7 to begin cycling when set to 1. To enable PWM7 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 6 to begin cycling when set to 1. To enable PWM6 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 5 to begin cycling when set to 1. To enable PWM5 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 4 to begin cycling when set to 1. To enable PWM4 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 3 to begin cycling when set to 1. To enable PWM3 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 2 to begin cycling when set to 1. To enable PWM2 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 1 to begin cycling when set to 1. To enable PWM1 onto the output pin, the pin control
registers must programmed accordingly.
Enables PWM channel 0 to begin cycling when set to 1. To enable PWM0 onto the output pin, the pin control
registers must programmed accordingly.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_PWM_CTRL field descriptions (continued)
Description
Freescale Semiconductor, Inc.