MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 851

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.3.2.1 Fractional Clock Divide Example, Divide by 3.5
As an example, if the desired divide value is 3.5, the digital approximation of 1/3.5 is
0.01001001 using a 8 bit fractional approximation. The most significant bit of the div field
in this case is logic 0, so the fractional divide mode is selected. The following sequence
indicates the first eight values of the fractional clock divider. The accumulated count is
simply the current value incremented by the value programmed in the div field on each
cycle.
When the carry out of the fractional count is one, a rising edge output pulse is initiated and
the remainder of the accumulator is preserved. The sub-fractional accumulated value is
considered to determine if the output edge should occur on the falling edge of the reference
clock or the rising edge of the reference clock to minimize the output clock jitter.
10.3.2.1.1 Fractional ClockDivide Example, Divide by 3/8
This example uses a 3-bit fractional accumulator to divide the reference clock input by 3/8.
There are 3 output clock edges produced for every eight input reference clock edges. An
output edge is generated on every cycle that the fractional accumulator carries out of the
most significant bit. Notice when the fractional component is .01, the output edge is shifted
and generated off the falling edge of the input reference clock. This is done to produce the
best output duty cycle that can be achieved based on the input reference clock frequency.
Freescale Semiconductor, Inc.
1. 0.01001001
2. 0.10010010
3. 0.11011011
4. 1.00100100 (carry out of MSB initiates an output clock edge)
5. 0.01101101
6. 0.10110110
7. 0.11111111
8. 1.01001000 (output edge initiated)
It is important to note that the nearest rising or falling edge of the
input reference clock frequency is used to approximate the rising
edge of the output clock domain. So, the output clock frequency
will jitter based on the input reference clock frequency and the
programmed fractional divide value.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Note
Chapter 10 Clock Generation and Control (CLKCTRL)
851