MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1984

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
1984
Reset
Reset
Bit
Bit
W
W
R
R
RSVD5
RSVD4
RSVD3
31 26
23 20
Field
UPI
UAI
TI1
TI0
25
24
19
18
17
AS
31
15
0
0
HW_USBCTRL_USBSTS 8008_0000h base + 144h offset = 8008_0144h
PS
30
14
0
0
Reserved.
General-Purpose Timer Interrupt 1 (GPTINT1).
This bit is set when the counter in the GPTIMER1CTRL (Non-EHCI) register transitions to 0. Writing a 1 to
this bit will clear it.
General-Purpose Timer Interrupt 0 (GPTINT0).
This bit is set when the counter in the GPTIMER0CTRL (Non-EHCI) register transitions to 0. Writing a 1 to
this bit will clear it.
Reserved.
USB Host Periodic Interrupt (USBHSTPERINT).
This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction
where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the
periodic schedule.
This bit is also set by the Host Controller when a short packet is detected AND the packet is on the periodic
schedule. A short packet is when the actual number of bytes received was less than the expected number
of bytes.
This bit is not used by the device controller and will always be 0.
USB Host Asynchronous Interrupt (USBHSTASYNCINT).
This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction
where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the
asynchronous schedule.
This bit is also set by the Host when a short packet is detected AND the packet is on the asynchronous
schedule. A short packet is when the actual number of bytes received was less than the expected number
of bytes.
This bit is not used by the device controller and will always be 0.
Reserved.
RCL
29
13
0
0
RSVD5
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HCH
28
12
0
0
HW_USBCTRL_USBSTS field descriptions
RSVD2
27
11
0
0
ULPII
26
10
0
0
RSVD1
TI1
25
0
0
9
TI0
SLI
24
0
0
8
Description
SRI
23
0
0
7
URI
22
0
0
6
RSVD4
AAI
21
0
5
0
SEI
20
0
4
0
Freescale Semiconductor, Inc.
UPI
FRI
19
0
0
3
UAI
PCI
18
0
0
2
RSVD3
UEI
17
0
0
1
NAKI
UI
16
0
0
0