MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1044

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
Re-
13.3.20 DCP Channel 1 Command Pointer Address Register
The DCP channel 1 current command address register points to the multiword descriptor
that is to be executed (or currently being executed). The channel may be activated by writing
the command pointer address to a valid descriptor in memory and then updating the
semaphore to a non-zero value. After the engine completes processing of a descriptor, the
next_ptr field from the descriptor is moved into this register to enable processing of the
next descriptor. All channels with a non-zero semaphore value will arbitrate for access to
the engine for the subsequent operation.
DCP Channel 1 is controlled by a variable sized command structure. This register points
to the command structure to be executed.
EXAMPLE
Address:
Re-
1044
set
set
Bit
Bit
W
W
pointer
R
R
RECOVERY_
31
31
0
0
TIMER
31 16
RSVD
Field
15 0
30
30
0
0
29
29
0
0
pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(1);
HW_DCP_CHn_CMDPTR_WR(1, v);
HW_DCP_CH0OPTS
HW_DCP_CH1CMDPTR
(HW_DCP_CH1CMDPTR)
28
28
0
0
Reserved, always set to zero.
This field indicates the recovery time for the channel. After each operation, the recover timer for the channel
is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate
another operation for the next packet in the chain until the recovery time has been satisfied. The timebase
for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
RSVD
24
24
0
0
23
23
0
0
HW_DCP_CH0OPTS field descriptions
22
22
8002_8000h base + 130h offset = 8002_8130h
0
0
21
8002_8000h base + 140h offset = 8002_8140h
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
// Write channel 1 command pointer
17
17
0
0
ADDR
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
RECOVERY_TIMER
0
0
0
0
9
9
0
0
8
8
// Read current command
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0