MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 904

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Linear Regulators
The power-up time is dependent on the VDDD/VDDA/VDDIO load and battery or VDD5V
voltage, but should be less than 100 ms. The VDDD//VDDAVDDIO load should be minimal
during power up to ensure proper startup of the DC-DC converter.
There is an integrated 5-K resistor that can be switched in between the VDDXTAL pin
and PSWITCH. If enabled using HW_RTC_PERSISTENT0_AUTO_RESTART, then the
device immediately begins the power-up sequence after power-down.
11.3.4 Power-Down Sequence
Power-down is also controlled by the DC-DC converters. When the DC-DC converter
detects a power-down event, it returns the device to the off state described above. The
power-down sequence is started when one of these events occur:
The HW_POWER_RESET_PWD_OFF bit disables all the power-down paths except for
the watchdog timer when it is set.
The lower 16 bits of the HW_POWER_RESET register can only be written, if the value
0x3E77 is placed in the unlock field.
An external capacitor on the PSWITCH can be used to prevent an unwanted power down
due to falling edges. This can also be disabled in HW_POWER_RESET_PWD_OFF register.
11.3.4.1 Powered-Down State
While the chip is powered down, the VDDIO, VDDD and VDDA rail are pulled down to
ground. The VDDIO rail is shorted to ground. The crystal oscillator and the RTC can
continue to operate by drawing power from the BATT pin. See
information about operating a crystal and the RTC in the powered-down state.
11.3.5 Reset Sequence
Figure 11-3
event can be triggered by unlocking the HW_POWER_RESET register and setting the
HW_CLKCTRL_RESET_DIG bit. This reset affects the digital logic only, although the
904
• HW_POWER_RESET_PWD bit set while the register is unlocked.
• Error condition occurs, as described in
• The watchdog timer expires while enabled.
• Fast falling edge (<10 ns) on PSWITCH pin.
shows a flowchart for the power-up, power-down and reset sequences. A reset
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Brownout/Error
Detection.
RTC Overview
Freescale Semiconductor, Inc.
for more