MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2223
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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The behavior of the SPDIF module during or after a FIFO underflow is programmable. On
detection of an underflow event, the SPDIF module sends the current sample for four frames
before muting (sending zeros) the data stream based on the configuration of
HW_SPDIF_FRAMECTRL_AUTO_MUTE. The final validity unit embedded within each
frame dictates whether the receiver processes the data within that frame.
HW_SPDIF_FRAMECTRL determines the behavior of this bit.
Freescale Semiconductor, Inc.
2x24 Right-Channel
Flow Control
2x24 Left-Channel
DMA Data
APBX Master
DMA Request
AHB Slave
Engine
FIFO
FIFO
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
ARM Core
APBX Clock Domain
Figure 36-1. SPDIF Transmitter Block Diagram
Shared DMA
AHB-to-APBX Bridge
AHB
AHB Master
SPDIF Programmable Registers
SPDIF Stream Control
HW_SPDIF_CTRL
HW_SPDIF_SRR
HW_SPDIF_FRAMECTRL
Request Generation
FIFO Control and
Data Formatting (16-Bit/24-Bit)
SRAM
Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF)
Divide
Clock Crossing
by n
HW_SPDIF_SRR_RATE
pcm_spdif_clk Domain
SPDIF Data Encoding
Dual-Edge Fractional
PLL
24-MHz
Divide
XTAL
Ratio
ROM
Osc.
Clock Divider
pcm_spdif_clk
SPDIF Data
480 MHz
CLKCTRL Module
Divider
Clock
Divide
by 4
2223
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