MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1940

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
The UART firmware will tell the hardware when to detect the baud rate. The Autobaud
Detection logic can be configured to detect RX baud rate each time a RX DMA is kicked
off, or just each time the firmware writes the START_BAUD_DETECT bit in the
AUTOBAUD register. Once the baud rate is found, it is loaded into the RX baud divisor
register, and optionally loaded into the TX baud divisor register. Refer to the AutoBaud
register for programming details.
30.2.3 UART Character Frame
Figure 30-2
illustrates the UART character frame.
UARTTXD
1 2
lsb
msb
stop bits
1
5 8 data bits
0
n
Parity bit
Start
if enabled
Figure 30-2. Application UART Character Frame
30.2.4 DMA Operation
The Application UART can generate a DMA request signal for interfacing with a Direct
Memory Access (DMA) controller. Two DMA channels are supported, one for transmit
and one for receive. Each channel has an associated 16-bit transfer counter for the number
of bytes to transfer. Each DMA request is associated with one to four data bytes. For APBX
DMA UART RX channel, the first PIO word in the DMA command is CTRL0. However,
for APBX DMA UART TX channel, the first PIO word in a DMA command is CTRL1.
At the end of a receive DMA block transfer, the status register indicates any error conditions.
If a timeout condition occurs in the middle of a receive DMA block transfer, then the UART
sends dummy data to the DMA controller until the transfer counter is decremented to zero.
A receive DMA can be setup to get the status of the previous receive DMA block transfer.
The status indicates the amount of valid data bytes in the previous receive DMA block
transfer.
30.2.5 Data Transmission or Reception
Data received or transmitted is stored in two 16-byte FIFOs, although the receive FIFO has
an extra four bits per character for status information.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1940
Freescale Semiconductor, Inc.