MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1982

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1982
RSVD1
Field
ASP
ASE
PSE
FS1
FS0
9 8
IAA
LR
10
7
6
5
4
3
2
Reserved.
Asynchronous Schedule Park Mode Count (OPTIONAL).
When S/W changes the USBMODE.CM to Host(11), this field defaults to 0x3 and is R/W. It contains a count
of the number of successive transactions the host controller is allowed to execute from a high-speed queue
head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. See Section
4.10.3.2 of the EHCI specification for full operational details.
Valid values are 0x1-0x3. Software must not write a 0 to this bit as this will result in undefined behavior. This
field is set to 0x3 in host mode; 0x0 in device mode.
Light Host/Device Controller Reset (OPTIONAL).
Not Implemented. This field will always be 0.
Interrupt on Async Advance Doorbell.
This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it
advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host
controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status
bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is 1, then
the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to
0 after it has set the Interrupt on Sync Advance status bit in the USBSTS register to 1. Software should not
write a 1 to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This
bit is only used in host mode. Writing a 1 to this bit when device mode is selected will have undefined results.
Asynchronous Schedule Enable.
Default 0.
This bit controls whether the host controller skips processing the Asynchronous Schedule.
0 = Do not process the Asynchronous Schedule.
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Only the host controller uses this bit.
Periodic Schedule Enable.
Default Ob.
This bit controls whether the host controller skips processing the Periodic Schedule.
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
Only the host controller uses this bit.
Bit 1 of Frame List Size field. See definition of bit FS0 for the complete definition.
Bit 0 of Frame List Size field.
The Frame List Size field (FS2, FS1, FS0) specifies the size of the frame list that controls which bits in the
Frame Index Register should be used for the Frame List Current index. Note that this field is made up from
USBCMD bits 15, 3 and 2. Default is 000b.
000b = 1024 ELEMENTS (4096 bytes) Default value.
001b = 512_ELEMENTS (2048 bytes).
HW_USBCTRL_USBCMD field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.