MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1320

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Winbond SPI Mode
If the SSP is enabled and there is valid data within the FIFO, the start of transmission is
signified by the SSn master signal being driven low, and MOSI output is enabled. After a
further one-half SSP_SCK period, both master and slave are enabled onto their respective
transmission lines. At the same time, the SSP_SCK is enabled with a falling edge transition.
Data is then captured on the rising edge and propagated on the falling edges of the SSP_SCK
signal.
After all bits have been transferred, in the case of a single word transmission, the SSn line
is returned to its idle high state one SSP_SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSn pin remains in its active low state, until
the final bit of the last word has been captured, and then returns to its idle state as described
above.
For continuous back-to-back transfers, the SSn pin is held low between successive data
words and termination is same as that of a single word transfer.
17.6 Winbond SPI Mode
The Winbond SPI mode is similar to Motorola's SPI mode when POLARITY = PHASE,
where data is sampled on the rising edge. In addition to serial 1-bit reads and writes, 2-bit
(dual) and 4-bit (quad) reads are supported. Only 8-bit word length is supported for dual
and quad read modes. See
to the bit position in the byte being transferred.
17.7 Texas Instruments Synchronous Serial Interface (SSI)
Figure 17-9
transmitted frame.
1320
Mode
shows the Texas Instruments synchronous serial frame format for a single
Figure 17-8. Fast Read Dual and Quad Output Diagram
CLK
IO
IO
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
0
1
6
7
Data Out 1
4
5
IO
3
0
2
Switches from Input to Output
Figure
0
1
6
7
Data Out 2
4
5
2
3
17-8. The numbers in the IO signal waveform correspond
1
0
6
7
Data Out 3
4
5
2
3
0
1
7
6
Data Out 4
5
4
2
3
1
0
CLK
IO
IO
IO
IO
0
1
2
3
5
4
6
7
Byte 1
0
1
3
2
IO
5
4
6
7
Byte 2
0
SwitchesfromInput to Out
0
1
3
2
4
5
6
7
Byte 3
0
2
3
1
4
5
6
7
Byte 4
Freescale Semiconductor, Inc.
0
2
3
1

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