MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2162

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
HW_PXP_S0SCALE_WR(0x20002000);
HW_PXP_S0OFFSET_WR(0x01000100);
ensure averaging versus pixel replication
Address:
Re-
34.4.14 Color Space Conversion Coefficient Register 0
This register contains color space conversion coefficients in two's compliment notation.
The Coeffient 0 register contains coeffients used in the color space conversion algorithm.
The Y and UV offsets are added to the source buffer to normalize them before the conversion.
C0 is the coeffient that is used to multiply the luma component of the data for all three RGB
components.
EXAMPLE
//
//
//
//
2162
set
Bit
W
R
HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset
HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4
HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3
YOFFSET
XOFFSET
31
0
The equations used for Colorspace conversion are:
RSVD2
RSVD1
31 28
27 16
15 12
Field
11 0
RSVD2
30
0
R = C0*(Y+YOFFSET)
G = C0*(Y+YOFFSET) + C3(U+UV_OFFSET) + C2(V+UV_OFFSET)
R = C0*(Y+YOFFSET) + C4(U+UV_OFFSET)
29
0
HW_PXP_S0OFFSET
(HW_PXP_CSCCOEFF0)
28
0
Reserved, always set to zero.
This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed
block offset which gets added to the scaled block address to determine source data for the scaling engine.
Reserved, always set to zero.
This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed
block offset which gets added to the scaled block address to determine source data for the scaling engine.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_PXP_S0OFFSET field descriptions
23
0
YOFFSET
22
0
8002_A000h base + C0h offset = 8002_A0C0h
21
0
// 1/2x scaling (0x2.000)
// half-pixel offset for 8x8 block size in both X and Y to
20
0
19
0
18
0
17
0
+ C1(V+UV_OFFSET)
16
0
15
0
Description
RSVD1
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
XOFFSET
0
6
0
5
0
4
3
0
0
2
0
1
0
0