MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 381

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

APBH DMA Channel 1 is controlled by a variable sized command structure. This register
points to the command structure currently being executed.
EXAMPLE
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(1);
register, since there is only one field
pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 1, CMD_ADDR);
multi-register bitfield read macro
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(1).CMD_ADDR;
bitfield of indexed register's struct
Address:
Re-
6.5.16 APBH DMA Channel 1 Next Command Address Register
The APBH DMA Channel 1 Next Command Address register contains the address of the
next multiword command to be executed. Commands are threaded on the command address.
Set CHAIN to 1 in the DMA command word to process command lists.
APBH DMA Channel 1 is controlled by a variable sized command structure. Software loads
this register with the address of the first command structure to process and increments the
Channel 1 semaphore to start processing. This register points to the next command structure
to be executed when the current command is completed.
EXAMPLE
HW_APBH_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure);
BF_WRn(APBH_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure);
HW_APBH_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure;
Freescale Semiconductor, Inc.
set
Bit
W
since there is only one field
bitfield write macro
of indexed register's struct
R
CMD_ADDR
31
0
Field
31 0
30
0
29
0
(HW_APBH_CH1_NXTCMDAR)
HW_APBH_CH1_CURCMDAR
28
0
Pointer to command structure currently being processed for channel 1.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_APBH_CH1_CURCMDAR field descriptions
24
0
23
0
22
0
21
0
20
0
8000_4000h base + 170h offset = 8000_4170h
19
0
18
0
17
CMD_ADDR
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
// write the entire register,
0
9
// or, use multi-register
// or, assign to bitfield
0
8
0
7
// read the whole
// or, use
// or, assign from
0
6
0
5
0
4
3
0
0
2
0
1
381
0
0