MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1596

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Unified DMA Block Guide
26.2.1.3 Modes of Operation
The primary modes of operation of the uDMA are described in this section:
26.2.1.3.1 Legacy Mode
While in legacy mode, the uDMA reads and generates Legacy Buffer Descriptors (LBD).
Additionally, great effort is made to ensure that support signals such as interrupts behave
consistently with the legacy programming model used with the FEC. This is the default
mode of operation.
26.2.1.3.2 Enhanced Mode
While in enhanced mode, the uDMA reads and generates Enhanced Buffer Descriptors
(EBD). The descriptors are based on the LBD but allow for the support of additional features
such as IEEE-1588 support, additional interrupts and error checking among other features.
While in this mode, there is no hard requirement that the programming model is consistent
with the legacy programming model; however where reasonable the same look and feel is
accomplished.
26.2.2 Functional Description
This section provides the detailed functional description of the uDMA. The uDMA is a data
mover between the FIFO interface and the bus master and vice-versa. Additionally, the
uDMA is responsible for formatting the data being transferred into and out of buffer
descriptors. Further, the uDMA is responsible for the generation of various control signals
(that is, interrupts) that may occur during the process. The uDMA is the key link for enabling
the legacy programming format of the FEC module to work with the ENET-MAC.
This section provides the technical details for the uDMA. Additional details required for
legacy mode compatibility is provided in the FEC specification (FEC_BlockGuide.pdf).
There are two FIFO interfaces, one for transmit and one for receive. Please refer to the
documentation in the reference section for the detailed specification for these FIFO interfaces.
1596
• Supports Legacy Buffer Descriptor programming models and functionality.
• Enables an Enhanced Buffer Descriptor programming model to support new Ethernet
• Legacy mode
• Enhanced mode
functionality.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.