MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1329

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

17.8.6 SD/MMC Clock Control
Freescale Semiconductor, Inc.
• DMA Over ow/Under ow The SSP should stop SCK if the FIFO is full or the FIFO
• Command Response Error The SD/MMC card returns a R1 status response after
• Command Response Time-Out If an expected response is not received within 64
• When SD/MMC block is idle, the serial clock (SCK) toggling will be based on the
• SCK runs any time that RUN is set and a data or command is active or pending. If a
• If CONT_CLKING_EN=0, SCK stops running if received command response status
• If CONT_CLKING_EN=0, SCK stops running if a data operation has timed out or a
• If CONT_CLKING_EN=0, SCK stops running after all pending commands and data
is empty during data transfer. So, a DMA underflow or overflow should not occur.
However, if it does due to some unforeseen problem, the FIFO_OVRFLW or
FIFO_UNDRFLW status bit is set in the SSP Status Register and asserts a CPU IRQ.
most commands. The SSP can compare the R1 response against a mask/reference pair.
If any of the enabled bits are set, then an error will occur. The SSP stops requesting
any DMAs, sets the RESP_ERR status flag, and asserts a CPU IRQ. The CPU can read
the SSP Status Register to see the RESP_ERR flag and read the HW_SSP_SDRESP0
register to get the actual response from the SD/MMC card. That response contains the
specific error information. Once the error is understood, the CPU can reset the DMA
channel and the SSP and re-try the operation or take some other action to recover or
inform the user of a non-recoverable error.
SCK cycles, then the command response has timed out. If this occurs, the SSP stops
any DMA requests, stops transferring data to the card, sets the RESP_TIME-OUT status
flag, and asserts the RESP_TIME-OUT_IRQ. The ISR should read the status register
to find that a command response time-out has occurred. It can then decide to reset the
DMA channel and SSP and re-try the operation.
value of CONT_CLKING_EN and SLOW_CLKING_EN. See HW_SSP_CMD0 register
description.
command has been sent and a response is expected, then SCK continues to run until
the response is received. If a data operation is active or if the DAT line is busy, then
SCK runs.
R1 indicates an error.
CRC error has occurred.
operations have completed. SCK restarts when a new command or data operation has
been requested.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 17 Synchronous Serial Ports (SSP)
1329