MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1639

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.3.11.6.2 Transmit Processing
For IPv6 transmission, the SHIFT16 function is supported to process 32-bit aligned
datagrams.
IPv6 has no IP header checksum therefore, the IP checksum insertion configuration is
ignored.
The protocol checksum will be inserted only if the next header of the IP header is a known
protocol (that is, TCP, UDP or ICMP). If a known protocol is detected, the checksum over
all bytes following the IP header is calculated and inserted in the correct position.
The pseudo-header checksum calculation is performed for TCP and UDP datagrams
accordingly.
26.3.12 Resets and Stop Controls
26.3.12.1 Hardware Reset
Setting the ECR(RESET) bit, resets the Ethernet controller and initializes all registers and
logic. This bit is self-clare.
26.3.12.2 Soft Reset
When ECR(ETHER_EN) is cleared, during operation, the following happens:
26.3.12.3 Graceful Stop
The following conditions lead to a graceful stop of the MAC transmit or receive datapaths.
A graceful stop means that any currently ongoing transactions are completed normally and
no further frames after that will be accepted. The MAC can resume from a graceful stop
without the need for a reset (for example, ECR(ETHER_EN) bit deassertion is not required).
Freescale Semiconductor, Inc.
• DMA, buffer descriptor and FIFO control logic are reset, including the buffer descriptor
• Transmission is terminated by asserting mii_tx_err to the PHY.
• The current FIFO write is terminated and all further data from the application is ignored.
• The current FIFO read is terminated.
and FIFO pointers.
All subsequent writes are ignored until re-enabled.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 26 Ethernet Controller (ENET)
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