MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1566

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Functional Description
25.4.8 Message Buffer Lock Mechanism
Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive
process. When the ARM reads the Control and Status word of an "active not empty" Rx
MB, FlexCAN assumes that the ARM wants to read the whole MB in an atomic operation,
and therefore it sets an internal lock flag for that MB. The lock is released when the ARM
reads the Free Running Timer (global unlock operation), or when it reads the Control and
Status word of another MB. The MB locking is done to prevent a new frame to be written
into the MB while the ARM is reading it.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the
array are programmed with the same ID, and FlexCAN has already received and stored
messages into these two MBs. Suppose now that the ARM decides to read MB number 5
and at the same time another message with the same ID is arriving. When the ARM reads
the Control and Status word of MB number 5, this MB is locked. The new message arrives
and the matching algorithm finds out that there are no MBs that are free to receive, so it
decides to override MB number 5. However, this MB is locked, so the new message can
not be written there. It will remain in the SMB waiting for the MB to be unlocked, and only
2.
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In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured
when the BCC bit is negated.
• If a Tx MB containing the lowest ID is deactivated after FlexCAN has scanned it, then
• There is a point in time until which the deactivation of a Tx MB causes it not to be
the message will be lost. Suppose, for example, that two MBs have a matching ID to
a received frame, and the user deactivated the first matching MB after FlexCAN has
scanned the second. The received frame is lost even if the second matching MB was
free to receive.
FlexCAN will look for another winner within the MBs that it has not scanned yet.
Therefore, it may transmit a MB with ID that may not be the lowest at the time because
a lower ID might be present in one of the MBs that it had already scanned before the
deactivation.
transmitted (end of move-out). After this point, it is transmitted but no interrupt is issued
and the Code field is not updated. In order to avoid this situation, the abort procedures
described in
The locking mechanism only applies to Rx MBs which have a code
different than INACTIVE ('0000') or EMPTY
MBs can not be locked.
Transmission Abort Mechanism
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Note
should be used.
2
('0100'). Also, Tx
Freescale Semiconductor, Inc.