MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1095

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

If the command is to be interrupted, it will be halted after completing the current burst,
stored and placed at the top of the queue, and the new command will be executed. As long
as the command queue is not full, new commands may continue to be inserted into the
command queue based on the placement rules, even at the head of the queue ahead of the
interrupted command. The top entry in the command queue will be executed next. Whenever
the interrupted command is resumed, it will start from the point at which it was interrupted.
Note that priority 0 commands will never be interrupted, so the user should set any commands
that should not be interrupted to priority 0. If supported by the port interfaces, setting the
swap_port_rw_same_en parameter will enable interleaving.
14.7 DDR PHY
The DDR PHY encapsulates all functionality required to interface to external DDR DRAM
devices into a single module. This module is used to control the off-chip data capture and
synchronization logic for the read data. This module performs the following functions:
14.7.1 High Level Block Diagram
EMI uses a slice-based approach for the DDR PHY. Each slice manages a byte (8-bit) of
data and it’s corresponding dqs and dm signals. A high level block diagram of the PHY is
provided below.
Freescale Semiconductor, Inc.
Active Command
• Contains all data registers used to launch data, address and control signals to the DDR
• Controls the off-chip data capture and synchronization logic for the read data.
• Includes a DLL for timing.
memory and the memory controller.
Priority
Lower
Lower
Lower
New Command
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Priority
Higher
Higher
Higher
Originating Port
for Commands
Different
Same
Same
Conflicts?
Yes
No
No
Chapter 14 External Memory Interface (EMI)
Current command continues
Will swap IF swap_en = 1 and
swap_port_rw_same_en = 1
Will swap IF swap_en = 1
Action
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