MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 866

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
866
ASM_EMIPORT_
CPU_DATA_AS_
APBHDMA_AS_
APBXDMA_AS_
TRAFFIC_JAM_
AUTO_CLEAR_
TRAFFIC_AS_
ASM_ENABLE
CPU_INSTR_
DIV_ENABLE
AS_ENABLE
AS_ENABLE
AS_ENABLE
SLOW_DIV
DCP_AS_
PXP_AS_
RSRVD2
RSRVD1
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
18 16
Field
15 6
30
29
28
27
26
25
24
23
22
21
20
19
Enable auto-slow mode based on DCP activity. 0 = Run at the programmed CLK_H frequency.
Enable auto-slow mode based on PXP activity. 0 = Run at the programmed CLK_H frequency.
Reserved
Enable auto-slow mode based on EMI axi0 port activity. 0 = Run at the programmed CLK_HS frequency.
Enable auto-slow mode based on APBH DMA activity. 0 = Run at the programmed CLK_H frequency.
Enable auto-slow mode based on APBX DMA activity. 0 = Run at the programmed CLK_H frequency.
Enable auto-slow mode when less than three masters are trying to use the AHB. More than three active
masters will engage the default mode. 0 = Run at the programmed CLK_H frequency.
Enable auto-slow mode based on AHB master activity. 0 = Run at the programmed CLK_H frequency.
Enable auto-slow mode based on with CPU Data access to AHB. 0 = Run at the programmed CLK_H
frequency.
Enable auto-slow mode based on with CPU Instruction access to AHB. 0 = Run at the programmed CLK_H
frequency.
Enable CLK_H auto-slow mode. When this is set, then CLK_H will run at the slow rate until one of the fast
mode events has occurred.
If this bit is set to one (1'b1), HW_CLKCTRL_HBUS_DIV is cleared to 1 automatically without S/W interaction
when wakeup interrupt event happens. This feature is to accelerate the waking up from Wait-For-Interrupt
Mode.
Note: This bit is not self-cleared. This feature is supposed to used when the clk_h is reduced to very low
frequency, for example, 24KHz.
Slow mode divide ratio. Sets the ratio of CLK_H fast rate to the slow rate.
0x0
0x1
0x2
0x3
0x4
0x5
Reserved
HW_CLKCTRL_HBUS field descriptions (continued)
BY1 — Slow mode divide ratio = 1
BY2 — Slow mode divide ratio = 2
BY4 — Slow mode divide ratio = 4
BY8 — Slow mode divide ratio = 8
BY16 — Slow mode divide ratio = 16
BY32 — Slow mode divide ratio = 32
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.