MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2094

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
33.4.9 LCDIF VSYNC Mode and Dotclk Mode Control Register1
This register is used to control the VSYNC signal in the VSYNC and DOTCLK modes of
the block.
2094
VSYNC_PULSE_
VSYNC_PULSE_
PERIOD_UNIT
DOTCLK_POL
ENABLE_POL
WIDTH_UNIT
VSYNC_OEB
VSYNC_POL
HSYNC_POL
HALF_LINE_
HALF_LINE
PRESENT
ENABLE_
RSRVD1
VSYNC_
WIDTH
MODE
23 22
Field
17 0
29
28
27
26
25
24
21
20
19
18
(HW_LCDIF_VDCTRL1)
0 means the VSYNC signal is an output, 1 means it is an input. Should be set to 0 in the DOTCLK mode.
0x0
0x1
Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby
making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK.
Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC
period. Set it to 1 to invert the polarity.
Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC
period. Set it to 1 to invert the polarity.
Default is data launched at negative edge of DOTCLK and captured at positive edge. Set it to 1 to invert the
polarity. Set it to 0 in DVI mode.
Default 0 active low during valid data transfer on each horizontal line.
Reserved bits. Write as 0.
Default 0 for counting VSYNC_PERIOD in terms of CLK_DIS_LCDIFn cycles. Set it to 1 to count in terms
of complete horizontal lines. CLK_DIS_LCDIFn cycles should be used in the VSYNC mode, while horizontal
line should be used in the DOTCLK mode.
Default 0 for counting VSYNC_PULSE_WIDTH in terms of CLK_DIS_LCDIFn cycles. Set it to 1 to count in
terms of complete horizontal lines.
Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the
HORIZONTAL_PERIOD field (i.e. VSYNC_PERIOD field plus half horizontal line), otherwise it is just
VSYNC_PERIOD. Should be only used in the DOTCLK mode, not in the VSYNC interface mode.
When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will
begin with half a horizontal line. When this bit is 1, all fields will end with half a horizontal line, and none will
begin with half a horizontal line.
Number of units for which VSYNC signal is active. For the DOTCLK mode, the unit is determined by the
VSYNC_PULSE_WIDTH_UNIT. If the VSYNC_PULSE_WIDTH_UNIT is 0 for DOTCLK mode,
VSYNC_PULSE_WIDTH must be less than HSYNC_PERIOD. For the VSYNC interface mode, it should be
in terms of number of CLK_DIS_LCDIFn cycles only.
HW_LCDIF_VDCTRL0 field descriptions (continued)
VSYNC_OUTPUT — The VSYNC pin is in the output mode and the VSYNC signal has to be generated
by the LCDIF block.
VSYNC_INPUT — The VSYNC pin is in the input mode and the LCD controller sends the VSYNC
signal to the block.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.