MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1268

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Memory to Memory (Loopback) Operation
16.3 Memory to Memory (Loopback) Operation
The BCH supports a memory-to-memory mode of operation where both the encoded and
decoded buffers reside in system memory. This can be useful for applications where data
must be protected by ECC, but the storage device does not reside on the GPMI bus.
The BCH operation in memory to memory mode is much simpler than in GPMI mode since
DMAs are not required to manage the operation. Instead, software simply writes the
HW_BCH_DATAPTR and HW_BCH_METAPTR with the addresses of the data and
metadata (auxiliary) buffers and the HW_BCH_ENCODEPTR with the address of the buffer
for encoded data. To initiate the operation, software simply sets the M2M_ENCODE and
M2M_ENABLE bits in the control register. The BCH can be programmed to either issue
an interrupt at the end of the operation or software may poll the status bits for completion.
Memory to memory decode operations work in a similar manner. The encoded data address
is written to the HW_BCH_ENCODEPTR and the data and meta pointers are written to
buffers that correspond to the desired decoded data addresses. To initiate a decode, software
must set the M2M_ENCODE bit to 0 while writing the M2M_ENABLE bit. Note that the
addresses written to the HW_BCH_DATAPTR, HW_BCH_METAPTR and
HW_BCH_ENCODEPTR registers should always be aligned on a 4 byte boundary. In other
words, the 2 lower bits of the address should always be written with zeros.
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i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 16-5. Memory-to-Memory Operations
flash format register. The number of status bytes will be computed by the
NBLOCKS+1. The status area will be padded with zeros to the next word
Status bytes are allocated based on the NBLOCKS programmed into the
Block 3
Block 7
Status
Status
3
0
0
Syndrome data written for debug purposes will follow the
Block 2
Block 6
Status
Status
end of the status block.
0
0
2
Metadata
boundary.
Block 1
Block 5
Status
Status
1
0
Block 4
Block 8
block 0
Status
Status
Status
0
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