MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1101

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Alternatively, read data can also be returned to core logic at edge number 1 of emi_clk, a
cycle prior to the example. In this scenario, you need to set the value of register
phy_ctrl_reg_0[26:24] and phy_ctrl_reg_2[3:0] to one number less. Then, the dfi_rddata
and dfi_rddata_valid would become valid one cycle earlier.
14.7.7 Write Data Path
The following figure illustrates the write data path.
Freescale Semiconductor, Inc.
6. In this example, read data d0,d1 getting valid before edge number 1 of emi_clk and is
synchronized at edge 2 of emi_clk. Both the setup and hold time requirement are met
which means that the read data could be fetched by core logic safely.
The benefit is that the read latency is shortened by one cycle,
which helps increase the system performance. But, there’s a timing
risk on the setup time. If the io_dq/dqs_in comes a little late, a
setup time violation can occur and the unexpected data is returned
to core logic, which can cause a system crash.
emi_clk
write data latch
@emi_clk domain
clk_wr
write data latch
@clk_wr domain
clk_wr
io_dq_out
write data muxed out
mux_sel = clk_wr
io_dqs_out
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
DRAM device capture write data by the edge of io_dqs_out
:
Figure 14-12. Write Data Path
1
NOTE
d0
d1
d0
d0
clk_wr delay = 1/4 cycle
d1
d2
d3
d1
d2
Chapter 14 External Memory Interface (EMI)
d2
d3
d3
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