MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 877

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.8.17 SAIF0 Clock Control Register (HW_CLKCTRL_SAIF0)
This register controls the divider that generates the Serial Audio Interface (SAIF0) clock.
Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_SAIF0_WR(BF_CLKCTRL_SAIF0_DIV(40));
Freescale Semiconductor, Inc.
BUSY_REF_CPU
BUSY_REF_EMI
DCC_RESYNC_
BUSY_SYNC_
BUSY_DCC_
BUSY_REF_
DIV_XTAL
RESYNC
RSRVD3
RSRVD2
RSRVD1
DIV_EMI
ENABLE
MODE
25 18
15 12
XTAL
Field
11 8
7 6
5 0
29
28
27
26
17
16
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0.
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 1.
This read-only bit field returns a one when there is a change in HW_CLKCTRL_EMI_SYNCE_MODE_EN
or when there is a change in HW_CLKCTRL_CLKSEQ_BYPASS_CPU and
HW_CLKCTRL_EMI_SYNCE_MODE_EN is set. When this bit returns a one, do not change the CPU or
EMI divider values.
Always set to zero (0).
Reserved.
Reserved.
Always set to zero (0).
This field controls the divider connected to the crystal reference clock, ref_xtal, that drives the CLK_EMI
domain when bypass IS selected.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
Always set to zero (0).
This field controls the divider connected to the ref_emi reference clock that drives the CLK_EMI domain
when bypass IS NOT selected. For changes to this field to take effect, the ref_emi reference clock must be
running.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_EMI field descriptions (continued)
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
877