MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 459

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

APBH DMA Channel 11 is controlled by a variable sized command structure. Software
loads this register with the address of the first command structure to process and increments
the Channel 11 semaphore to start processing. This register points to the next command
structure to be executed when the current command is completed.
Address:
Re-
6.5.87 APBH DMA Channel 11 Command Register
The APBH DMA Channel 11 command register specifies the cycle to perform for the current
command chain item.
The command register controls the overall operation of each DMA command for this channel.
It includes the number of bytes to transfer to or from the device, the number of APB PIO
command words included with this command structure, whether to interrupt at command
completion, whether to chain an additional command to the end of this one and whether
this transfer is a read or write DMA transfer.
Freescale Semiconductor, Inc.
set
Bit
W
R
CMD_ADDR
31
0
Field
31 0
30
0
29
0
(HW_APBH_CH11_CMD)
HW_APBH_CH11_NXTCMDAR 8000_4000h base + 5E0h offset = 8000_45E0h
28
0
Pointer to next command structure for Channel 11.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_APBH_CH11_NXTCMDAR field descriptions
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
CMD_ADDR
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
459
0
0