MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1025

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.3.1 DCP Control Register 0 (HW_DCP_CTRL)
The CTRL register contains controls for the DCP module.
HW_DCP_CTRL: 0x000
HW_DCP_CTRL_SET: 0x004
HW_DCP_CTRL_CLR: 0x008
HW_DCP_CTRL_TOG: 0x00C
The Control register contains the primary controls for the DCP block. The present bits
indicate which of the sub-features of the block are present in the hardware. The context
control bits control how the DCP utilizes it's context buffer and the gather residual writes
bit controls how the master handles writing misaligned data to the bus. Each channel and
the color-space converter contains an independent interrupt enable.
EXAMPLE
Freescale Semiconductor, Inc.
8002_81C0
8002_81D0
8002_8160
8002_8170
8002_8180
8002_8190
8002_81A0
8002_81B0
8002_81E0
8002_81F0
8002_8400
8002_8410
8002_8420
8002_8430
Absolute
address
(hex)
HW_DCP_CTRL_SET(BM_DCP_CTRL_SFTRST);
HW_DCP_CTRL_CLR(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE);
DCP Channel 1 Status Register (HW_DCP_CH1STAT)
DCP Channel 1 Options Register (HW_DCP_CH1OPTS)
DCP Channel 2 Command Pointer Address Register
(HW_DCP_CH2CMDPTR)
DCP Channel 2 Semaphore Register (HW_DCP_CH2SEMA)
DCP Channel 2 Status Register (HW_DCP_CH2STAT)
DCP Channel 2 Options Register (HW_DCP_CH2OPTS)
DCP Channel 3 Command Pointer Address Register
(HW_DCP_CH3CMDPTR)
DCP Channel 3 Semaphore Register (HW_DCP_CH3SEMA)
DCP Channel 3 Status Register (HW_DCP_CH3STAT)
DCP Channel 3 Options Register (HW_DCP_CH3OPTS)
DCP Debug Select Register (HW_DCP_DBGSELECT)
DCP Debug Data Register (HW_DCP_DBGDATA)
DCP Page Table Register (HW_DCP_PAGETABLE)
DCP Version Register (HW_DCP_VERSION)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DCP memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Chapter 13 Data Co-Processor (DCP)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0201_0000h
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