MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2208

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
In 16-bit operation, sample pairs are packed with the right samples occupying the upper
halfword and left samples the lower halfword of the FIFO entries.
For 17-bit to 24-bit operation, each FIFO entry contains a sample that is right-justified (LSB
in bit 0).
The first sample DMA-ed to the FIFO at the start of operation should always be a left
sample, followed by a right, and so on. If four or six channel pairs are enabled, samples
should be grouped with all left samples first, followed by all right samples (for example,
front left, surround left, then center, followed by front right, surround right then LFE, and
so on). As long as data resides within the FIFO(s), valid sample pairs continue to be output.
If the FIFO(s) ever underflow or overflow, an interrupt occurs. At this point, the system
software should shut down the SAIF, clear the FIFO(s), and then cleanly resume operation
because there is not a way to prevent left/right swap of the PCM channels after this point.
If the FIFO does underflow, null samples are output until valid data once again resides
within the bottom of the FIFO. Any PCM value that is written to a full FIFO is discarded,
preventing the top entry from be overwritten.
When the RUN bit is cleared at the end of operation, all PCM data corresponding to one
sample collection (either two, four, or six channel pairs) that are currently being transmitted
are allowed to complete before operation ceases and the BITCLK, LRCLK, and SDATA
pins stop transitioning.
Alternately, software can be used to maintain the FIFO(s) if the DMA is not used, either
by responding to an interrupt that is issued whenever an empty FIFO entry exists, or by
polling a FIFO status bit.
35.2.3 Receive Operation
If the APBX DMA is to collect PCM data from the SAIF FIFO(s), the user first configures
its corresponding DMA channel and allocates the buffer(s) where PCM data is to be recorded.
Next the SAIF control register is initialized, selecting the frame format and number of
channel pairs, selecting whether the SAIF is BITCLK/LRCLK master or slave, clearing the
CLKGATE bit, and setting the RUN bit.
Once running, the SAIF either waits until the BITCLK and LRCLK pins begin to transition
(slave mode) or begins to toggle BITCLK and LRCLK (master mode). In either case, once
an LRCLK edge that corresponds to the start of a left sample is detected, the SAIF
frame-control logic begins to assemble the sample in its serial shift register. Each time the
LRCLK pin toggles, a new sample is pushed to the FIFO(s).
In 16-bit operation, sample pairs are packed with the right samples occupying the upper
halfword and left samples the lower halfword of the FIFO entries.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2208
Freescale Semiconductor, Inc.