MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1087

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.5.7 Arbitration Examples
To demonstrate arbitration behavior, consider the following system:
An example with these settings is shown in
only win arbitration when there are no priority 1 requests. Also note that each arbitration
counter only increments, and always increments, when a request of that priority is processed.
Cycle 5 demonstrates the always condition of counter incrementing: even though the
arbitration was won by the other port of highest priority instead of the one in the counter,
the counter still increments.
Freescale Semiconductor, Inc.
Cycle
• Four ports.
• Ports 0 and 1 request only at priority 1. Ports 2 and 3 request only at priority 2.
• All ports have bandwidth allocations of 100% and the bandwidth overflow bit is set to
10
11
0
1
2
3
4
5
6
7
8
9
‘b1. (Bandwidth will not affect arbitration.)
Current Arbitra-
PG 1
tion Counter
0
0
1
9
1
1
0
0
0
0
1
1
Table 14-8. Priority Round-Robin without Bandwidth Consideration
PG 2
2
2
2
2
2
3
3
2
2
2
2
3
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Port 0
—
—
—
—
—
—
—
Y
Y
Y
Y
Y
PG1 = Priority Group 1 and PG2 = Priority Group 2
Ports Requesting
Port 1
—
—
—
—
—
—
—
—
—
Y
Y
Y
Port 2
—
—
—
—
Y
Y
Y
Y
Y
Y
Y
Y
Port 3
Table
—
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
14-8. Note that priority 2 requests will
Queue Full
Command
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Chapter 14 External Memory Interface (EMI)
Winner of Arbitra-
None
None
None
tion
P0
P1
P0
P2
P0
P3
P0
P2
P3
Next Arbitration
PG 1
0
1
0
1
1
1
0
0
0
1
1
1
Counter
PG 2
2
2
2
2
3
3
2
2
2
2
3
2
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