MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 847

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.2.2 Logical Diagram of Clock Domains
Freescale Semiconductor, Inc.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
PLL1
PLL0
System PLL0, Multi-Output PLL
ENET_CLK
-------------------------------------
Each output configurable for
-------------------------------------
XTAL _CLK24M
RING_CLK24M
Ring Oscillator
XTAL _CLK32K
Crystal Clock
Figure 10-1. Logical Diagram of Clock Domains
frequency and bypass.
System PLL1, USB1
24.000 MHz
24.000 MHz
Crystal Clock
32.768 kHz /
32.0 kHz
ENET_MII_PHY0
ICG
ICG
ICG
ICG
ICG
ICG
ICG
PAD
PLL 480M
HW_CLKCTRL_ENET_CLK_OUT_EN
Phase Div
Phase Div
Phase Div
Phase Div
Phase Div
Phase Div
PLL 480M
Phase Div
enet_rmii_clk_in
0
1
gl
CLK_ENET_OUT
ref_pll
ref_gpmi
ref_hsadc
ref_cpu
ref_emi
ref_io0
ref_io1
ref_pix
HW_CLKCTRL_PLL1CTRL
HW_CLKCTRL_PLL0CTRL
ref_xtal
HW_RTC_PERSISTENT0_CLKSOURCE
HW_CLKCTRL_XTAL
ref_pll
ref_gpmi
ref_hsadc
ICG
ref_pix
ref_io1
PLL2 50M
ref_io0
ref_xtal
ref_xtal
ref_xtal
768
ref_emi
ref_xtal
ref_xtal
ref_xtal
ref_xtal
ref_xtal
HW_CLKCTRL_SPDIF
enet_rmii_clk_in
ref_enet_pll
HW_CLKCTRL_HBUS
Dynamic Power
ref_pll
HW_CLKCTRL_CPU
HW_CLKCTRL_CPU
HW_CLKCTRL_EMI
HW_CLKCTRL_EMI
HW_CLKCTRL_XTAL
HW_CLKCTRL_ENET_TIME_SEL
HW_CLKCTRL_EMI
ICG
ICG
HW_CLKCTRL_HBUS
ref_xtal
Adjust
ICG
HW_CLKCTRL_DIS_LCDIF0
Fixed Divider
Int
Int/Frac
Int
Int
HW_CLKCTRL_HSADC
HW_CLKCTRL_SSP0(1)
HW_CLKCTRL_GPMI
HW_CLKCTRL_SSP2(3)
ICG
HW_CLKCTRL_SAIF
ICG
ICG
ICG
HW_CLKCTRL_ETM
ICG
4
HW_CLKCTRL_XBUS
ICG
ICG
ICG
6 bit
10 bit
HW_CLKCTRL_XTAL
(2 Clock Gate control bits)
6 bit
6 bit
4 bit
Fixed Divider
Chapter 10 Clock Generation and Control (CLKCTRL)
4 bit
Int/Frac
Int/Frac
Int/Frac
Int/Frac
Frac
via ENET Controller H/W
Int/Frac
750
Int/Frac
EN1
10 bit
HW_CLKCTRL_ENET
13 bit
9 bit
9 bit
10 bit
7 bit
EN2
16 bit
1 to 31
via HW_SPDIF_SRR
6 bit
ICG
5 bit
Int
Frac
Fixed Divider
Int
Others
Analog
Digital
Digital
Digital
16
HSADC
HW_CLKCTRL_ENET
DIV
9 bit
HW_CLKCTRL_EMI_SYNC_MODE_EN
HW_CLKCTRL_CPU & INTERRUPT WAIT circuit
Xtal Only
Xtal or PLL
PLL Only
HW_CLKCTRL_ENET
via FLEXCAN Controller H/W
CLK_FLEXCAN_NOGATE (x2)
ICG
ICG
ICG
ICG
Unless otherwise shown, all
multiplexers are controlled via
HW_CLKCTRL_CLKSEQ
Within CLKCTRL
ICG
ICG
ICG
ICG
ICG
ICG
ICG
ICG
ICG
ICG
ICG
UTMI1_CLK480M
UTMI0_CLK480M
CLK_PCMSPDIF
CLK_SSP (X2)
CLK_SSP (X2)
CLK_SAIF (X2)
CLK_ENET_OUT
Legend
CLK_H_ENET_SWI
CLK_HSADC
CLK_H_FLEXCAN0(x2)
CLK_DIS_LCDIF
CLK_FLEXCAN (x2)
CLK_H_FLEXCAN_IPG(x2)
CLK_LRADC2k
CLK_H_MAC(x2)
CLK_GPMI
CLK_ANA24M
CLK_P_NG
CLK_PWM24M
CLK_ETM
CLK_ENET_TIME
CLK_UART
CLK_RTC32K
CLK_ENET_RMII
CLK_H
CLK_OCROM
CLK_32K
CLK_MAC0_RX
CLK_MAC0_TX
CLK_X
CLK_EMI
CLK_P
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