MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1399

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Address:
Re-
19.4.40 AHB Statistics Control Register
The AHB Statistics Control Register selects which AHB Masters on each Layer of the AHB
subsystem are enabled to contribute to the statistics calculations.
This register is to enable performance monitoring for the corresponding AHB master in
layers
EXAMPLE
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
L3_MASTER_
PRODUCT_
REVISION
31
31
0
0
SELECT
RSVD0
RSVD0
31 16
CODE
31 24
23 16
Field
15 8
Field
7 0
30
30
0
0
29
29
1
0
HW_DIGCTL_CHIPID
HW_DIGCTL_AHB_STATS_SELECT
C330h
RSVD0
(HW_DIGCTL_AHB_STATS_SELECT)
28
28
0
0
This read-only bit field returns 0x2800, which identifies the generation from which the part is derived.
Reserved.
This read-only bit field always reads back the mask revision level of the chip.
Reserved.
Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 3 arbiter for the
corresponding AHB master. Bits [7:6] are currently reserved and should not be set
0x1
0x2
27
27
1
0
26
26
0
0
PRODUCT_CODE
HW_DIGCTL_AHB_STATS_SELECT field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
APBHDMA — Select APBH DMA Master.
APBXDMA — Select APBX DMA Master.
25
25
0
0
24
24
0
0
23
HW_DIGCTL_CHIPID field descriptions
23
0
0
L3_MASTER_SELECT
22
22
0
0
8001_C000h base + 310h offset = 8001_C310h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
8001_C000h base + 330h offset = 8001_
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
L2_MASTER_SELECT
14
14
0
0
13
13
0
0
RSVD0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
L1_MASTER_SELECT
0
0
6
6
0
0
5
5
REVISION
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1399
0
0
0
0