MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1844

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1844
800F_831C
800F_832C
800F_833C
800F_840C
800F_8314
800F_8318
800F_8320
800F_8324
800F_8328
800F_8330
800F_8334
800F_8338
800F_8400
800F_8404
800F_8408
800F_8410
800F_8414
800F_8418
800F_8500
Absolute
address
(hex)
ENET SWI Port 0 incoming frames discarded due to
mismatching or missing VLAN id
(HW_ENET_SWI_IDISC_VLAN0)
ENET SWI Port 0 incoming frames discarded due to missing
vlan tag (HW_ENET_SWI_IDISC_UNTAGGED0)
ENET SWI Port 0 incoming frames discarded (after learning)
as port is configured in blocking mode
(HW_ENET_SWI_IDISC_BLOCKED0)
ENET SWI Port 1 Outgoing frames discarded due to output
Queue congestion (HW_ENET_SWI_ODISC1)
ENET SWI Port 1 incoming frames discarded due to
mismatching or missing VLAN id
(HW_ENET_SWI_IDISC_VLAN1)
ENET SWI Port 1 incoming frames discarded due to missing
vlan tag (HW_ENET_SWI_IDISC_UNTAGGED1)
ENET SWI Port 1 incoming frames discarded (after learning)
as port is configured in blocking mode
(HW_ENET_SWI_IDISC_BLOCKED1)
ENET SWI Port 2 Outgoing frames discarded due to output
Queue congestion (HW_ENET_SWI_ODISC2)
ENET SWI Port 2 incoming frames discarded due to
mismatching or missing VLAN id
(HW_ENET_SWI_IDISC_VLAN2)
ENET SWI Port 2 incoming frames discarded due to missing
vlan tag (HW_ENET_SWI_IDISC_UNTAGGED2)
ENET SWI Port 2 incoming frames discarded (after learning)
as port is configured in blocking mod
(HW_ENET_SWI_IDISC_BLOCKED2)
ENET SWI Interrupt Event Register (HW_ENET_SWI_EIR)
ENET SWI Interrupt Mask Register (HW_ENET_SWI_EIMR)
ENET SWI Pointer to Receive Descriptor Ring
(HW_ENET_SWI_ERDSR)
ENET SWI Pointer to Transmit Descriptor Ring
(HW_ENET_SWI_ETDSR)
ENET SWI Maximum Receive Buffer Size
(HW_ENET_SWI_EMRBR)
ENET SWI Receive Descriptor Active Register
(HW_ENET_SWI_RDAR)
ENET SWI Transmit Descriptor Active Register
(HW_ENET_SWI_TDAR)
ENET SWI Learning Records A (0) and B (1)
(HW_ENET_SWI_LRN_REC_0)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_SWI memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc.
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0020h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
29.9.97/1923
29.9.98/1924
29.9.99/1924
29.9.100/1925
29.9.101/1925
29.9.102/1926
29.9.103/1926
29.9.104/1927
29.9.105/1927
29.9.106/1928
29.9.107/1928
29.9.108/1929
29.9.109/1930
29.9.110/1931
29.9.111/1932
29.9.112/1932
29.9.113/1933
29.9.114/1933
29.9.115/1934
Section/
page