MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2072

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
CLK_DIS_LCDIFn cycles (47 KHz with a 24 MHz CLK_DIS_LCDIFn). The timings are
not automatically adjusted if the CLK_DIS_LCDIFn frequency changes, so it may be
necessary to adjust the timings if CLK_DIS_LCDIFn changes.
In the MPU interface mode, the HW_LCDIF_CTRL_ BYPASS_COUNT bit must be 0.
The RUN bit is cleared automatically once the LCDIF has received/transmitted all the data
as per the HW_LCDIF_TRANSFER_COUNT register and has completed the transfer to
the panel. The current transfer can be cancelled/aborted if the RUN bit is manually made
0.
33.2.6.1 Code Example to Initialize the LCDIF in MPU Write Mode
// Note: Common initialization steps in
Initializing the LCDIF
must also be
// executed along with the following code
BF_CS1(LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that the
// idle state for LCD_RS signal is high, regardless of the
// programming of the DATA_SELECT register.
BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE);
BF_CS1 (LCDIF_CTRL, READ_WRITEB, 0);
BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in MPU mode
BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 1);//Only if LCD controller implements a busy line
BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2);
//Values based
// on CLK_DIS_LCDIFn frequency and timing requirements of
controller.
// Note that these register must be non-zero for correct operation.
BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240); //For a 320 RGB x 240 display
BF_CS1 (LCDIF_CTRL, RUN, 1);
The LCDIF is now ready to receive data through DMA writes to the HW_LCDIF_DATA
register or fetch data directly from memory as a bus master. Also, note that, while in soft
DMA mode, the software will need to poll the FIFO STATUS bits to ensure that it does
not overflow the LCDIF data buffers. When LCDIF is done transmitting H_COUNT x
V_COUNT pixels, it will stop, turn off the RUN bit and assert the cur_frame_done interrupt.
33.2.7 VSYNC Interface
The VSYNC interface uses the same protocol as the MPU interface, with an additional
signal VSYNC at the frame rate of the display, as shown in
Figure
33-11. It is used in the
moving picture display mode where data has to be written to the internal LCD buffer at a
speed higher than the display rate and displayed in synchronization with the VSYNC signal.
This mode is selected by setting the VSYNC_MODE bit in HW_LCDIF_CTRL register.
The VSYNC signal is programmable for period, polarity and direction. Many other
programmable parameters are shared with the MPU interface. The VSYNC_OEB bit in
HW_LCDIF_VDCTRL0 register indicates whether the display controller will send the
VSYNC signal, or whether it should be generated by LCDIF. The timing of the VSYNC
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2072
Freescale Semiconductor, Inc.