MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1263

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

16.2.2 Flash Page Layout
The BCH supports a fully programmable flash page layout. The BCH maintains four
independent layout registers that can describe four completely different NAND devices or
layouts. When the BCH initiates an operation, it selects one of the layouts by using the chip
select as an index into the HW_BCH_LAYOUTSELECT register the determines which
layout should be used for the operation.
Three possible (generic) flash layout schemes are supported, as indicated in
(In each case, the metadata size may also be programmed to 0 bytes). Metadata may either
be combined with the first block of data or the size of the first data block can be programmed
to 0 to allow the metadata to be protected by its own ECC parity bits.
Each layout is determined by a pair of registers that define the following parameters:
Freescale Semiconductor, Inc.
• Flash read operations can read the entire page or the first block on the page.
• The BCH also supports a memory-to-memory mode of operation that does not require
• DATA0_SIZE: Indicates the number of data bytes in the first block on the page (this
the use of DMA or the GPMI.
should not include parity or metadata bytes). This should be set to 0 when the metadata
is to be covered separately with its own ECC. This must be a multiple of 4 bytes.
Size=10B
Block 0
ECC=4
meta
meta
meta
32B
10B
10B
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Size=516B
Size=522B
ECC=14
ECC=16
Block 0
Block 0
484B
Size=512B
512B
d0
ECC=14
d0
Block 1
Figure 16-3. FLASH Page Layout Options
512B
d0
Size=516B
Size=512B
ECC=14
ECC=16
Block 1
Block 1
516B
512B
Size=512B
Combined Metadata & Block 0, unbalanced ECC coverage
d1
Combined Metadata & Block 0, balanced ECC coverage
ECC=14
d1
Block 2
512B
d1
Separate ECC over Metadata
Size=516B
Size=512B
ECC=14
ECC=16
Block 2
Block 2
516B
512B
d2 2
d2
512B
d2
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
516B
dn-1
512B
dn-1
512B
dn-1
516B
512B
dn
dn
512B
dn
Figure
16-3.
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