MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1068

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

EMI AHB and AXI Interface
1. Since all commands from an AHB-bridged port use a single thread ID, this option is not applicable for AHB-bridged ports.
2. For a native AXI port, read and write commands may be interleaved. For an AHB-bridged port, a write command will not be
placed ahead of a read command from the same port. However, a read command may be placed ahead of a write command.
An incoming AXI transaction is mapped into a core logic-level transaction, then synchronized
from the AXI clock domain to the core logic clock domain and stored in the AXI port FIFOs.
Each instruction consists of an address, size, length and thread ID. Since a port may utilize
multiple thread IDs, the source ID that is used in the core logic is a combination of both the
port and thread information. This concatenation occurs in the Arbiter and this source ID is
used in the placement logic. From the AXI FIFOs, the transaction is presented to the Arbiter
which arbitrates requests from all ports and forwards a single transaction to the core logic.
14.4.2.2 AHB Signal to AXI Signal Translation
14.4.2.3 Configured Options
Each AXI port has been defined for the requirements of the intended system. The configured
options are:
1068
SINGLE
INCR
WRAP4
INCR4
WRAP8
INCR8
WRAP16
INCR16
(ahb_hburst)
• Type of interface to the EMI core clock (emi_clk)
• Width of the ID
All ports are clock domain programmable relative to the emi_clk. These ports initialize
in asynchronous operation, but can be changed by programming the associated
axiY_fifo_type_reg parameter. For more information on the programming of this
parameter, refer to section
crossing when operating in any of the non-synchronous modes.
Each port is configured with a thread ID of 10 bits.
AHB
‘b000
‘b001
‘b010
‘b011
‘b100
‘b101
‘b110
‘b111
FIXED
INCR
WRAP
INCR
WRAP
INCR
WRAP
INCR
(axi_awburst / axi_arburst)
AXI Burst type
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
‘b00
‘b01
‘b10
‘b01
‘b10
‘b01
‘b10
‘b01
Table 14-2. Burst Type Translation
Port
Clocking. Asynchronous FIFOs handle the clock domain
1 word
4 words
4 words
4 words
8 words
8 words
16 words
16 words
(axi_awlen / axi_arlen)
AXI Burst length
‘b0000
‘b0011
‘b0011
‘b0011
‘b0111
‘b0111
‘b1111
‘b1111
Freescale Semiconductor, Inc.