MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1094

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Core Command Queue with Placement Logic
14.6.2.2 High-Priority Command Swapping
Commands are assigned priority values to ensure that critical commands are executed more
quickly in the memory controller than less important commands. Therefore, it is desirable
that high-priority commands pass into the core logic as soon as possible. The placement
algorithm takes priority into account when determining the order of commands, but still
allows a scenario in which a high-priority command sits waiting at the top of the command
queue while another command, perhaps of a lower priority, is in process.
The high-priority command swapping feature allows this new high-priority command to be
executed more quickly. If the user has enabled the swapping function through the swap_en
parameter, then the entry at the top of the command queue will be compared with the current
command in progress. If the command queue’s top entry is of a higher priority (not the same
priority), and it does not have an address, source ID or write buffer conflict with the current
command being executed, then the original command will be interrupted.
For this memory controller, an additional check is performed before a read command is
interrupted. If the read command in progress and the read command at the top of the
command queue is from the same port, then the executing command will only be interrupted
if the swap_port_rw_same_en parameter is set to ‘b1. If this parameter is cleared to ‘b0, a
read command from the same port as a read command in progress, even with a higher
priority and without any conflicts, would remain at the top of the command queue while
the current command completes.
Note: All write commands from a single port, even with different source IDs, will be executed
in order. Therefore, two write commands from the same port will never be swapped
regardless of the settings of the swap_en and swap_port_rw_same_en parameters.
Note: Priorities are assigned to read commands based on the settings in the axiY_r_priority
parameters. While all read commands from a port are assigned the same priority when
placed in the command queue, their priorities may change over time through command
aging. While uncommon, it is possible that a higher-priority read command may be at the
top of the command queue while a lower-priority read command is executing. The behavior
of the system in this scenario is based on the value of the swap_en and
swap_port_rw_same_en parameters.
Refer to the following table for details:
Table 14-10. Swapping Behavior
Active Command
New Command
Originating Port
Conflicts?
Action
Priority
Priority
for Commands
Higher
Lower
Same or Different
Yes or No
Current command continues
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1094
Freescale Semiconductor, Inc.